Method and apparatus of evaluating layer matching deviation based on CAD information

ABSTRACT

An apparatus of evaluating a layer matching deviation based on CAD information of the invention, is provided with means for storing CAD data and a function of displaying to overlap a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a design CAD image read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying to overlap a pattern image of the semiconductor device formed on the wafer and the design CAD image of the pattern, in addition thereto, a function capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern formed at a later step by displaying to overlap a design CAD image of the pattern formed at the later step.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an apparatus for evaluatinglayer matching deviation in a step of fabricating a semiconductordevice.

[0002] In fabricating a semiconductor device (hereafter, abbreviatedsimply as semiconductor fabrication), first, a pattern of asemiconductor is designed and the pattern is memorized to store as CADdata. Based thereon, a photomask is fabricated and the semiconductorelement is not fabricated respectively as a single member thereof but anumber of devices are simultaneously fabricated on one sheet of asemiconductor wafer. Therefore, the photomask is drawn with patterns ofa number the same as that of devices fabricated on the one sheet ofsemiconductor wafer, however, when the wafer is printed by the masksimply aligned with the same images, the completely same circuit patternis not photographed at a central portion and a peripheral portion of thewafer. This is because warp is necessarily accompanied by beinginfluenced by aberration or the like of an optical system. Therefore,according to a circuit pattern, there is designed a pattern taking amargin anticipating a safety factor in consideration of the aberrationof the optical system actually used in transcription such that thecircuit constitution becomes normal in all the area on the transcribedwafer. The transcription of the pattern is executed not for a singlelayer but by being overlapped over a number of layers in a thicknessdirection of the wafer. Further, patterns of different layers are formedby being transcribed by different masks and a circuit is constituted foran individual device and therefore, there is needed a connection amongthe patterns of the different layers. Therefore, shapes of the patternsamong the different masks and positional relationship thereofconstitutes an important yield factor in fabricating the semiconductordevice. Further, as described above, a number of the devices are formedon the wafer and it is necessary that the shapes of the respectivepatterns and the positional relationship thereamong, are converged in anallowable range (within margin) of the design standard both at thecentral portion and the peripheral portion. Particularly, since thelarge amount of semiconductors are fabricated based on the mask andtherefore, finishing accuracy thereof is an important item directlyinfluencing on the yield of the product.

[0003] Conventionally, control of the yield dependent upon the shape ofthe wafer pattern in a step of fabricating a semiconductor device iscarried out by using SEM (scanning electron microscope) for lengthmeasurement. According to the method, at each step of fabricating steps,the pattern shape is measured by SEM and the shape of the pattern ischecked to thereby control the yield. According to the method, thepattern shape can be checked at respective steps, however, matching of apattern formed at a step thereafter cannot be evaluated and therefore,in this regard, it is the current state that the matching is carried outin synthetic evaluation including pattern failure over steps by electricmeasurement or the like after finishing a final step. According toevaluation executed after finishing the final step, it is difficult tospecify at which portion of which step the failed portion is caused andtherefore, there is brought about a situation in which enormous time andlabor is taken in a necessary modifying operation.

SUGARY OF THE INVENTION

[0004] The present invention relates to an apparatus of evaluating alayer matching deviation having a function capable of determiningwhether a pattern of a semiconductor device falls in a allowable rangeof design including a relative positional relationship with a pattern ofa later step to be able to carry out instruction to improve yield at anearly stage of steps of fabricating a semiconductor device.

[0005] An apparatus of evaluating a layer matching deviation based onCAD information of the invention, is provided with means for storing CADdata and a function of displaying to overlap a scanning microscope imageof a pattern of a semiconductor device formed on a wafer and a designCAD image read from the storing means and a function of evaluatingacceptability of formation of the pattern by displaying to overlap apattern image of the semiconductor device formed on the wafer and thedesign CAD image of the pattern, in addition thereto, a function capableof evaluating acceptability of formation of the pattern also with regardto a shape and positional relationship with a pattern formed at a laterstep by displaying to overlap a design CAD image of the pattern formedat the later step.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIGS. 1A-1C show a high magnification microscope image of an aimedpattern in which FIG. 1A shows a pattern image formed on a wafer, FIG.1B shows a CAD image of the pattern and FIG. 1C shows to overlap the twoimages on a display.

[0007]FIGS. 2A-2B show a high magnification microscope image of an aimedpattern in which FIG. 2A shows a CAD image displayed by overlapping apattern to be formed at a successive step or thereafter to the aimedpattern and FIG. 2B shows a CAD image formed in FIG. 2A to overlap on aformed pattern at a current time point on the display.

[0008]FIG. 3A displays to overlap a CAD pattern of a via layer forshortcircuiting a fist metal layer and a second metal layer and patterncontour lines formed at different chips (A, B, C) and sampled fromobservation images of the first metal layer and FIG. 3B is a graphshowing a corresponding relationship of a rate of bringing the firstmetal layer and the via layer into contact with each other and yield ofthe device.

[0009]FIG. 4 is a block diagram showing a basic constitution of anapparatus used in the invention.

[0010]FIG. 5 is a diagram showing an example of displaying a resultevaluated by the invention as a wafer map.

DESCRIPTION OF THE REFERENCE NUMERALS AND SIGNS

[0011]1 Navigation apparatus, 11 CAD apparatus, 12 CAD storing portion,13 Pattern image data acquiring portion, 14 Image memory, 15 Edgesampling portion, 16 CAD line segment cutting portion, 17 Buffer memory,18 Comparing and matching portion, 19 Stage position correcting portion,2 Stage, 3 Pattern observing apparatus (display), 4 Sample (wafer), 7Position controlling unit, S1, S11, D1, D2, D3 Signals

DETAILED DESCRIPTION OF THE INVENTION

[0012] According to an apparatus of observing a wafer pattern forevaluating acceptability of forming a pattern, there is observed aportion of a pattern constituting an observation object disposed withinan area of about several through several tens * square in a patternformed on a wafer by enlarging the portion with high magnification andtherefore, it is necessary to highly accurately position an observationfield of vision of the wafer pattern observing apparatus to a desiredobservation position on a wafer pattern. Hence, conventionally, as anavigation method for the positioning, there is generally usedso-to-speak CAD navigation for specifying the observation object byusing a CAD apparatus and by development of a semiconductor fabricatingtechnology in recent years, a dimension of a pattern formed on a waferbecomes a submicron order and in order to observe such an ultra finepattern, there has been used a wafer pattern observing apparatus havinga high magnification of a multiplication factor of several tensthousands.

[0013] According to the invention, there is used a wafer patternobserving apparatus having the CAD navigation function, the apparatus isprovided with a function of displaying to overlap a scanning microscopeimage of a pattern of a semiconductor device formed on the wafer and adesign CAD image read from storing means, the apparatus is not onlyprovided with a function of evaluating acceptability of forming thepattern by displaying to overlap a pattern image of the semiconductordevice formed on the wafer and the design CAD image of the pattern, butalso a function capable of reading a design CAD image of a patternformed at a later step by sampling the design CAD image from the storingmeans and displaying the design CAD image to overlap the currentmicroscope image, thereby, there can be checked and evaluated also ashape and positional relationship of the formed current pattern and thepattern to be formed in the later step. The invention is characterizedin that not only it is checked whether the pattern which has alreadybeen formed falls in an allowable range of the design pattern but alsothe shape and positional relationship with the pattern to be formed atthe later step can be checked previously. By enabling to grasp a shapedefect at an early time point, occurrence of a failure thereafter can beprevented beforehand by feeding back improvement instruction to a stepof forming an aimed pattern. Further, information of the shape defectprovided at the time point can be reflected to promotion of yield of aproduct by feeding forward the information in the form of correcting theposition of the pattern in the later step or the like to thereby correctthe pattern and can also be reflected to a change in the design of themask pattern per se. All of the counter measures contribute to promotionof the yield of the device.

[0014]FIG. 1A shows an image of a microscope having high magnificationspecifying a certain pattern in one chip on a wafer and FIG. 1B shows aCAD image of the pattern. FIG. 1C shows the two images to overlap on adisplay. Numeral 21 denotes a SEM image of a first metal layer, 22denotes a CAD image of a first metal layer, 23 denotes an overlappedimage of a CAD image and a SEM image. It is found that the pattern imageobserved in the example matches excellently with the design CAD imagealthough only corner portions thereof are rounded. Further, thephenomenon of rounding the corner portions is a well-known phenomenon inthe field of photolithography and the deformation is anticipated fromthe start. Now, it has been found that the pattern formed in theobservation is constituted by a proper shape matching with the CAD imageand it is observed by an image shown in FIGS. 2A-2B whether the patternis proper also in a relationship with a pattern formed in a later step.Numeral 24 denotes a CAD image of a second metal layer, 25 denotes a vialayer. FIG. 2A is a CAD image displaying to overlap the pattern to beformed in a successive step and thereafter to an aimed pattern and FIG.2B shows an image displaying the CAD image of FIG. 2A on a display tooverlap onto a formed pattern at a current time point. The patternadopted in FIGS. 1A-1C and FIGS. 2A-2B, is designed such that a secondrectangular metal layer is formed above a metal layer in an L-like shapeand a via layer for shortcircuiting the two patterns is formed at endportions of the two metal layers. When observed by FIG. 2B, the CADimage of the second metal layer of the later step, overlaps the firstmetal layer 23 which has already been formed and also a CAD image of thevia layer 25 for shortcircuiting the two metal layers is positioned atthe area overlapping the two metal layers. It is found that formation ofthe first metal layer 23 is proper also in the positional relationshipwith the pattern at the later step.

[0015] In actual steps of fabricating a semiconductor in which a numberof chips are simultaneously fabricated, there is mixed with a chip inwhich formation of a pattern is improper and there is needed acountermeasure for resolving the improperness. FIG. 3A shows to overlapthe CAD pattern of the via layer 25 for shortcircuiting the first metallayer and the second metal layer, and pattern contour lines sampled fromobserved images of the first metal layer formed at different chips (A,B, C). A first metal layer pattern A is formed as designed and a contactratio thereof with the via layer is as excellent as 100%. A first metallayer pattern B is formed to be slightly smaller than the design CADdiagram and a contact ratio 31 thereof with the via layer is equal to orsmaller than 50%. In the case of a first metal layer pattern C, thepattern is formed to be far smaller than the design CAD diagram and acontact rate thereof with the via layer becomes 0%. In such a case, thefirst metal layer and the second metal layer cannot be conducted witheach other and the chip constitutes a failed device when fabricated asit is. There is recognized a corresponding relationship between yield ofthe device and the rate of bringing the first metal layer and the vialayer in contact with each other and there is established a relationshipas shown by FIG. 3B from the data.

[0016] Next, an explanation will be given of an embodiment and aprocessing flow of the invention in reference to FIG. 4. FIG. 4 is ablock diagram showing a basic constitution of an apparatus used in theinvention and numeral 1 designates a navigation apparatus for specifyingan observation field of vision of a desired position. As the navigationapparatus 1, there is used a constitution presented in Japanese PatentApplication No. 2000-214846 “Navigation method and apparatus forobserving pattern of semiconductor apparatus” which has been filedpreviously by the inventors, that is, a navigation apparatus “comprisingdesignating means for designating a predetermined portion, memory meansfor storing CAD data in correspondence with a pattern, low magnificationpattern image data acquiring means for acquiring low magnificationpattern image data of a semiconductor device by matching an observationposition of the pattern observing apparatus by low magnification to makecenter of observation of the predetermined portion fall in anobservation field of vision in response to the designating means, meansfor outputting edge line segment data by sampling an edge of the patternbased on the low magnification pattern image data, means for providingCAD line segment data in correspondence with the low magnificationpattern image data in response to the designating means and the memorymeans, means for calculating a deviation amount between the center ofobservation and a center of the observation field of vision by comparingthe CAD line segment data and the edge line segment data, and means forexecuting a position control such that the center of observation and thecenter of the observation field of vision coincide with each other bycompensating for a stage error of a stage based on the deviation amount”in order to observe by enlarging the predetermined portion of thepattern of the semiconductor device set to the stage by the patternobserving apparatus while enlarging in a high magnification.

[0017] Numeral 11 designates a CAD apparatus for designating navigationand numeral 12 designates a CAD storing portion for storing patterninformation. Numeral 13 designates a low magnification pattern imagedata acquiring portion and when an observing portion is designated fromthe CAD apparatus 11 constituting the navigation designating portion, inresponse to a designating signal S11 outputted thereby, the lowmagnification pattern image data acquiring portion outputs a positionsetting signal S1 to thereby execute positioning of a sample stage 2.Meanwhile, in response to a magnification setting signal S12, a patternobserving apparatus 3 is set with low magnification and lowmagnification pattern image data D1 provided by the pattern observingapparatus, is transmitted to the pattern image data acquiring portion 13and is stored to an image memory 14. Further, at an edge samplingportion 15, based on low magnification pattern image data stored to theimage memory 14, there is carried out an edge sampling processing andedge line segment data D2 is outputted.

[0018] Meanwhile, at a CAD line segment data cutting portion 16, inresponse to the designating signal S11 from the navigation designatingportion 11, CAD line segment data D3 in correspondence with thedesignated observation portion, is read from the CAD storing portion 12and is stored to a buffer memory 17. At a comparing and matching portion18, there are compared the edge line segment data D2 from the edgesampling portion 15 and the CAD line segment data D3 from the buffermemory 17, a matching processing is executed and a deviation amount ofcalculated. Deviation amount data D4 indicating a deviation amountprovided by the comparing and matching portion 18, is transmitted to astage position correcting portion 19, at the portion, there is formed aposition correcting signal S2 for moving the stage 2 such that a centerof observation in the low magnification image and a center of an actualobservation field of vision of the pattern observing apparatus 3,coincide with each other and is transmitted to a position control unit7. Above-described is navigation operation for observing the pattern ofa semiconductor device to observe the predetermined position of thepattern of a semiconductor device 4 set to the stage by enlarging thepredetermined portion by high magnification by the pattern observingapparatus. By the positioning, a high magnification image of thepredetermined portion is caught at a center of a screen and therefore,the magnification of the microscope is changed to high magnification andthe invention is executed.

[0019] The high magnification image is acquired, transmitted to thepattern image data acquiring portion 13 and is stored to the imagememory 14. Further, at the edge sampling portion 15, there is carriedout the edge sampling processing based on the high magnification patternimage data stored to the image memory 14 and the edge line segment dataD2 is outputted. On the other hand, the CAD segment of the predeterminedportion is cut and stored to the buffer memory 17 and therefore, the twoline segment images are displayed to overlap by the pattern observingapparatus 3. The positional relationship is accurately matched by theprevious navigation and therefore, measurement of the deviation amountis executed on the screen. Further, for example, when the contour lineof the first metal layer constituting the edge line segment data, isprovided by the contour lines 32 designated by notation A, B or C asshown by FIG. 3A, the aimed pattern is evaluated in accordance with thedeviation amount of the CAD line segment image. Further, by overlappingthe pattern microscope image as indicated by FIG. 2A, with the CAD imageand a CAD image of a related pattern at a successive step, matching ofthe positional relationship displayed on the pattern observing apparatus3 is evaluated. Operation of evaluating these is carried out with regardto a predetermined pattern in a specified chip, further, by selecting apertinent sample chip from a respective area such as a central portionor a peripheral portion on the wafer. A result of evaluation which iscarried out for the sample can be displayed on the pattern observingapparatus 3 in a mode of a map display of the wafer as shown by FIG. 5.Incidentally, a rectangle in FIG. 5 displays a position of an observedand evaluated pattern and a deviation amount of the portion.

[0020] According to the method of evaluating the layer matchingdeviation based on the CAD information of the invention, the design CADdata is stored, the electron microscope image of the pattern of thesemiconductor device formed on the wafer and the stored design CAD imageare read, overlapped and displayed on the display, thereby,acceptability of formation of the pattern is evaluated and further, bydisplaying to overlap the pattern to be formed in the later step anddesign CAD image of other pattern related thereto, there is evaluatedacceptability of formation of the pattern with regard to a relativerelationship with the other pattern formed in the later step andtherefore, the acceptability of the formation of the pattern in therespective fabricating step of the semiconductor can be confirmed at therespective step, improvement instruction at an early stage can becarried out for a defect and therefore, there is achieved a significanteffect in promoting the yield. Early discovery can not only be reflectedto improvement in forming an aimed pattern by correcting a mask or thelike but also can be reflected to a change in design of a CAD diagramconstituting a basis thereof, or the adjustment of a position of theother pattern formed in the later step and there can be expected afurther effect in promoting the yield of the semiconductor device.

[0021] According to the apparatus of evaluating the layer matchingdeviation based on the CAD information of the invention, there isprovided the means for sampling the contour segment from the microscopeimage in evaluating the acceptability of formation of the pattern bydisplaying the electron microscope image of the pattern of thesemiconductor device formed on the wafer and the stored design CAD imageto overlap on the display by reading the two images, the pattern imageof the semiconductor device formed on the wafer, adopts the patterncontour line segment sampled by the contour line segment sampling meansand therefore, there can easily be executed evaluation of the layermatching deviation based on the positioning and the CAD information inthe field of vision of the microscope by comparing with the microscopeimage per se.

[0022] Further, in order to catch the pattern image of the predeterminedportion at the center of the field of vision by the microscope havinghigh magnification, by providing the navigation apparatus comprising themeans for providing the low magnification microscope image bycontrolling the stage based on the position information, the means forcalculating the deviation amount by the CAD line segment information andthe matching processing on the low magnification microscope image andmeans for executing positioning of the stage based on the calculateddeviation amount, the aimed pattern of the predetermined position caneasily be caught as the microscope image having the high magnification.

What is claimed is:
 1. A method of evaluating a layer matching deviationbased on CAD information, the method comprising: storing design CAD dataof a semiconductor device formed on a semiconductor wafer; and readingthe design CAD data of a pattern of the semiconductor device andoverlapping the design CAD data with an electron microscope image of thepattern formed on the semiconductor wafer on a display so as to evaluateacceptability of the formation of the pattern.
 2. A method of evaluatinga layer matching deviation based on CAD information, the methodcomprising: storing design CAD data of a semiconductor device formed ona semiconductor wafer; reading the design CAD data of a first pattern ofthe semiconductor device and overlapping the design CAD data with anelectron microscope image of the first pattern formed on thesemiconductor wafer on a display so as to evaluate acceptability of theformation of the pattern; and further overlapping a design CAD image ofa second pattern which is formed in a later step and related to thefirst pattern so as to evaluate acceptability of formation of the firstpattern with regard to a relative relationship with the second pattern3. An apparatus of evaluating a layer matching deviation based on CADinformation, the apparatus comprising: means for storing design CADdata; means for displaying to overlap a scanning microscope image of apattern of a semiconductor device formed on a wafer with a design CADimage read from the storing means on a display, wherein acceptability offormation of the first pattern is evaluated by displaying to overlap afirst pattern image of the semiconductor device formed on the wafer withthe design CAD image of the first pattern, and the acceptability of theformation of the first pattern also is evaluated with regard to arelative relationship with a second pattern which is formed in a laterstep and related to the first pattern by displaying to overlap thesecond pattern with the overlapped images.
 4. The apparatus ofevaluating a layer matching deviation based on CAD information accordingto claim 2, further comprising means for sampling a contour line segmentfrom the microscope image, wherein the pattern image of thesemiconductor device formed on the wafer is a pattern contour linesegment sampled by the contour line segment sampling means.
 5. Theapparatus of evaluating a layer matching deviation based on CADinformation according to claim 3 having a navigation apparatuscomprising means for providing a low magnification microscope image bycontrolling a stage based on position information, means for calculatinga deviation amount by information of a CAD line segment and a matchingprocessing on the low magnification microscope image in order to catch apattern image of a predetermined portion at a center of a field ofvision by a microscope having high magnification.
 6. The apparatus ofevaluating a layer matching deviation based on CAD information accordingto claim 4 having a navigation apparatus comprising means for providinga low magnification microscope image by controlling a stage based onposition information, means for calculating a deviation amount byinformation of a CAD line segment and a matching processing on the lowmagnification microscope image in order to catch a pattern image of apredetermined portion at a center of a field of vision by a microscopehaving high magnification.